/******************************************************************************
 * (C) Copyright 
 * FILE NAME:    driver_clock.c
 * DESCRIPTION:
 * 
 * DATE BEGUN:   
 * BY:        
 * PRODUCT NAME:
 * APPLICATION:
 * TARGET H/W:   MC9S12G48
 * DOC REF:
 *****************************************************************************
 */

/*****************************************************************************
** #include 
*****************************************************************************/
#include "system.h"
#include "drv_clock.h"
#include "drv_clock_cfg.h"
/*****************************************************************************
** #define
*****************************************************************************/


/*****************************************************************************
** typedef
*****************************************************************************/


/*****************************************************************************
** global variable
*****************************************************************************/


/*****************************************************************************
** static variables
*****************************************************************************/


/*****************************************************************************
** static constants
*****************************************************************************/


/*****************************************************************************
** static function prototypes
*****************************************************************************/


/*****************************************************************************
** function prototypes
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/****************************************************************************/
/****************************************************************************/
/**
 * Function Name: drv_clockInit
 * Description: 1. Enable PLL
 *              2. Set bus clock to 8MHz/16MHz
 *
 * Param:   none
 * Return:  none
 * Author: 
 ****************************************************************************/
void drv_clockInit(void)
{
#if (SYS_CLOCK_SOURCE == OSC_8MHZ) 
	
		CPMUPROT = 0x26U; // Disable protection of clock configuration registers // 
	
		/* CPMUCLKS: PLLSEL=1,system clock are derived from PLLCLK, fbus = fPLL/2 */
		CPMUCLKS_PLLSEL = 1U; /* Enable the PLL to allow write to divider registers */
		
		/* CPMUCLKS: PSTP=1 */
		/* Oscillator continues to run in Stop Mode (Pseudo Stop Mode), option to run RTI and COP.*/
		CPMUCLKS_PSTP = 1U; 
		
		/* COP clock source is ACLK(10kHz) derived from a trimmable internal RC-Oscillator */
		CPMUCLKS_COPOSCSEL1 = ON;
		
		CPMUCLKS_PCE = ON; /* COP continues running during Pseudo Stop Mode */
		
		CPMUOSC_OSCE = 1U; /* Enable the oscillator */ 
		
		while(CPMUFLG_UPOSC == 0U) /* Wait until the oscillator is qualified by the PLL */
		{
		   ;
		}
		
		/* CPMUREFDIV: REFFRQ1=1,REFFRQ0=0,REFDIV3=0,REFDIV2=0,REFDIV1=0,REFDIV0=0 */
		/* REFCLK Frequency Ranges: REFFRQ[1:0]:10, 6MHz < fREF <= 12MHz
		** fREF = fOSC/(REFDIV + 1) = 8MHz/(0+1)= 8MHz
		*/		
		CPMUREFDIV = 0x80U; 	/* Set the divider register */
		  
		/* CPMUSYNR: VCOFRQ1=0,VCOFRQ0=0,SYNDIV5=0,SYNDIV4=0,SYNDIV3=1,SYNDIV2=1,SYNDIV1=1,SYNDIV0=1 */
		/* fVCO If PLL has locked (LOCK=1), 	
		** 32MHz <= fVCO <= 50MHz.
		** fVCO = 2??fREF ??(SYNDIV + 1) = 2 x 8MHz x (1 + 1) = 32MHz.
		** The following rules help to achieve optimum stability and shortest lock time:
		** Use lowest possible fVCO / fREF ratio (SYNDIV value). so set the lowest SYNDIV.
		** Use highest possible REFCLK frequency fREF.	
		*/
		CPMUSYNR = 0x01U;
		//----------------------------------------------------------------------------------------- 	
    #if (SYSTEM_BUS_CLOCK == CLK_8MHZ)    
			  
			/* CPMUPOSTDIV: POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=0,POSTDIV0=0 */
			/* fPLL = fVCO/(POSTDIV + 1)= 32MHz/(1+1)= 16MHz
			** fbus = fPLL/2 = 8MHz;
			*/
			CPMUPOSTDIV = 0x01U; /* Set the post divider register */		   
				   
    #elif (SYSTEM_BUS_CLOCK == CLK_16MHZ)
		  
			/* CPMUPOSTDIV: POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=0,POSTDIV0=0 */
			/* fPLL = fVCO/(POSTDIV + 1)= 32MHz/(0+1)= 32MHz
			** fbus = fPLL/2 = 16MHz;
			*/
			CPMUPOSTDIV = 0x00U; /* Set the post divider register */			
	 
    #else
        #error "MAC SYSTEM_BUS_CLOCK is NOT defined !"    /* system clock Defines not found! */   
    #endif
		//------------------------------------------------------------------------------------------
	
		/* CPMUPLL: FM1=0,FM0=0 */
		CPMUPLL = 0x00U;	 /* Set the PLL frequency modulation */
	
		while((CPMUFLG_LOCK == 0U) || (CPMUFLG_UPOSC == 0U) ) 
		{		
			/* Wait until the PLL is within the desired tolerance of the target frequency */
		}  
	
		CPMUFLG = 0xFF;
	
	#if (RTI_CLOCK_SOURCE == IRC_1MHZ) 
		
			CPMUCLKS_RTIOSCSEL = 0U; /* rti clock is IRCCLK */ 
	
	#else 
			CPMUCLKS_RTIOSCSEL = 1U; /* rti clock is OSCCLK */ 
	
	#endif
		
		CPMUPROT = 0x00U;	/* Enable protection of clock configuration registers */	
					 
		/* Common initialization of the CPU registers */
		/* CPMUINT: LOCKIE=0,OSCIE=0 */
		CPMUINT &= (UINT8)(~(UINT8)0x12U);	
					 
		/* CPMULVCTL: LVIE=0 */
		/* Low-Voltage Interrupt disable */
		CPMULVCTL &= (UINT8)(~(UINT8)0x02U);
							   
		/* IRQCR: IRQEN=0 */
		/* disable IRQ */
		IRQCR &= (UINT8)(~(UINT8)0x40U);
		
		/*Disable ECLK output, Disable ECLK x 2 output*/
		ECLKCTL = 0xC0;
	
#elif (SYS_CLOCK_SOURCE == OSC_16MHZ) 
	
		CPMUPROT = 0x26U; // Disable protection of clock configuration registers // 
	
		/* CPMUCLKS: PLLSEL=1,system clock are derived from PLLCLK, fbus = fPLL/2 */
		CPMUCLKS_PLLSEL = 1U; /* Enable the PLL to allow write to divider registers */
	
		/* CPMUCLKS: PSTP=1 */
		/* Oscillator continues to run in Stop Mode (Pseudo Stop Mode), option to run RTI and COP.*/
		CPMUCLKS_PSTP = 1U; 
	
		/* COP clock source is ACLK(10kHz) derived from a trimmable internal RC-Oscillator */
		CPMUCLKS_COPOSCSEL1 = ON;
	
		CPMUCLKS_PCE = ON; /* COP continues running during Pseudo Stop Mode */
	
		
		CPMUOSC_OSCE = 1U; /* Enable the oscillator */ 
	
		while(CPMUFLG_UPOSC == 0U) /* Wait until the oscillator is qualified by the PLL */
		{
		   ;
		}
	
		/* CPMUREFDIV: REFFRQ1=1,REFFRQ0=0,REFDIV3=0,REFDIV2=0,REFDIV1=0,REFDIV0=0 */
		/* REFCLK Frequency Ranges: REFFRQ[1:0]:11, fREF > 12MHz
		** fREF = fOSC/(REFDIV + 1) = 16MHz/(0+1)= 16MHz
		*/		
		CPMUREFDIV = 0xC0U; 	/* Set the divider register */
		  
		/* CPMUSYNR: VCOFRQ1=0,VCOFRQ0=0,SYNDIV5=0,SYNDIV4=0,SYNDIV3=1,SYNDIV2=1,SYNDIV1=1,SYNDIV0=1 */
		/* fVCO If PLL has locked (LOCK=1),
		** 32MHz <= fVCO <= 50MHz.	  
		** fVCO = 2??fREF ??(SYNDIV + 1) = 2 x 16MHz x (0 + 1) = 32MHz.
		** The following rules help to achieve optimum stability and shortest lock time:
		** Use lowest possible fVCO / fREF ratio (SYNDIV value). so set the lowest SYNDIV.
		** Use highest possible REFCLK frequency fREF.
		*/
		CPMUSYNR = 0x00U;
		
		//----------------------------------------------------------------------------------------- 	
#if (SYSTEM_BUS_CLOCK == CLK_8MHZ)    
			  
			/* CPMUPOSTDIV: POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=0,POSTDIV0=0 */
			/* fPLL = fVCO/(POSTDIV + 1)= 32MHz/(1+1)= 16MHz
			** fbus = fPLL/2 = 8MHz;
			*/
			CPMUPOSTDIV = 0x01U; /* Set the post divider register */		   
			 
				   
#elif (SYSTEM_BUS_CLOCK == CLK_16MHZ)
		  
			/* CPMUPOSTDIV: POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=0,POSTDIV0=0 */
			/* fPLL = fVCO/(POSTDIV + 1)= 32MHz/(0+1)= 32MHz
			** fbus = fPLL/2 = 16MHz;
			*/
			CPMUPOSTDIV = 0x00U; /* Set the post divider register */  
	
#else
    #error "MAC SYSTEM_BUS_CLOCK is NOT defined !"    /* system clock Defines not found! */   
#endif
		//------------------------------------------------------------------------------------------
	
		/* CPMUPLL: FM1=0,FM0=0 */
		CPMUPLL = 0x00U;	 /* Set the PLL frequency modulation */
	
		while((CPMUFLG_LOCK == 0U) || (CPMUFLG_UPOSC == 0U) ) 
		{		
			/* Wait until the PLL is within the desired tolerance of the target frequency */
		}  
	
		CPMUFLG = 0xFF;
	
	#if (RTI_CLOCK_SOURCE == IRC_1MHZ) 
		
			CPMUCLKS_RTIOSCSEL = 0U; /* rti clock is IRCCLK */ 
	
	#else 
			CPMUCLKS_RTIOSCSEL = 1U; /* rti clock is OSCCLK */ 
	
	#endif
	
		CPMUPROT = 0x00U;	/* Enable protection of clock configuration registers */	
					 
		/* Common initialization of the CPU registers */
		/* CPMUINT: LOCKIE=0,OSCIE=0 */
		CPMUINT &= (UINT8)(~(UINT8)0x12U);	  
					 
		/* CPMULVCTL: LVIE=0 */
		/* Low-Voltage Interrupt disable */
		CPMULVCTL &= (UINT8)(~(UINT8)0x02U);
							   
		/* IRQCR: IRQEN=0 */
		/* disable IRQ */
		IRQCR &= (UINT8)(~(UINT8)0x40U);
	
		/*Disable ECLK output, Disable ECLK x 2 output*/
		ECLKCTL = 0xC0;
	
																
#elif (SYS_CLOCK_SOURCE == IRC_1MHZ) 
	
		/*	System clock initialization */
		/* CPMUPROT: PROT=0 */
		CPMUPROT = 0x26U; /* Disable protection of clock configuration registers */  
		
		/* CPMUCLKS: PLLSEL=1,system clock are derived from PLLCLK, fbus = fPLL/2 */
		CPMUCLKS_PLLSEL = 1U;	 /* Enable the PLL to allow write to divider registers */
		
		/* CPMUCLKS: PSTP=0 */
		CPMUCLKS_PSTP = 0U; /* Oscillator is disabled in Stop Mode (Full Stop Mode).*/
		
		/* COP clock source is ACLK(10kHz) derived from a trimmable internal RC-Oscillator */
		CPMUCLKS_COPOSCSEL1 = ON;
		
		CPMUCLKS_PCE = ON;	 //COP continues running during Pseudo Stop Mode
		
		CPMUOSC_OSCE = 0U;	 /* disable external oscillator */
		//----------------------------------------------------------------------------------------- 	
    #if (SYSTEM_BUS_CLOCK == CLK_8MHZ)
	
		/* CPMUSYNR: VCOFRQ1=0,VCOFRQ0=0,SYNDIV5=0,SYNDIV4=0,SYNDIV3=1,SYNDIV2=1,SYNDIV1=1,SYNDIV0=1 */
		/* fVCO If PLL has locked (LOCK=1),
		** 32MHz <= fVCO <= 50MHz.
		** fVCO = 2??fREF ??(SYNDIV + 1) = 2 x 1MHz x (15 + 1) = 32MHz. 
		** The following rules help to achieve optimum stability and shortest lock time:
		** Use lowest possible fVCO / fREF ratio (SYNDIV value). so set the lowest SYNDIV.
		** Use highest possible REFCLK frequency fREF.	  
		*/
			CPMUSYNR = 0x0FU;	
			  
			/* CPMUPOSTDIV: POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=1,POSTDIV0=1 */
			/* fPLL = fVCO/(POSTDIV + 1)= 32MHz/(1+1)= 16MHz
			** fbus = fPLL/2 = 8MHz;
			*/
			CPMUPOSTDIV = 0x01U; /* Set the post divider register */		   
			
			/* CPMUPLL: FM1=0,FM0=0 */
			CPMUPLL = 0x00U;					 /* Set the PLL frequency modulation */
			  
			while(CPMUFLG_LOCK == 0U) 
			{		
				/* Wait until the PLL is within the desired tolerance of the target frequency */
			}	
			
    #elif (SYSTEM_BUS_CLOCK == CLK_16MHZ)	  
	
			/* CPMUSYNR: VCOFRQ1=0,VCOFRQ0=0,SYNDIV5=0,SYNDIV4=0,SYNDIV3=1,SYNDIV2=1,SYNDIV1=1,SYNDIV0=1 */
			/* fVCO If PLL has locked (LOCK=1),
			** fVCO = 2??fREF ??(SYNDIV + 1) = 2 x 1MHz x (15 + 1) = 32MHz.
			*/
			CPMUSYNR = 0x0FU;
			  
			/* CPMUPOSTDIV: POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=1,POSTDIV0=1 */
			/* fPLL = fVCO/(POSTDIV + 1)= 32MHz/(0+1)= 32MHz
			** fbus = fPLL/2 = 16MHz;
			*/
			CPMUPOSTDIV = 0x00U; /* Set the post divider register */			 
			
			/* CPMUPLL: FM1=0,FM0=0 */
			CPMUPLL = 0x00U;		/* Set the PLL frequency modulation */
			  
			while(CPMUFLG_LOCK == 0U) 
			{		
				/* Wait until the PLL is within the desired tolerance of the target frequency */
			} 
			
    #else
        #error "MAC SYSTEM_BUS_CLOCK is NOT defined !"    /* system clock Defines not found! */   
    #endif 
		//-----------------------------------------------------------------------------------------
	
	#if (RTI_CLOCK_SOURCE == IRC_1MHZ) 
		
			CPMUCLKS_RTIOSCSEL = 0U; /* rti clock is IRCCLK */ 
	
	#else 
			CPMUCLKS_RTIOSCSEL = 1U; /* rti clock is OSCCLK */ 
	
	#endif
		
		CPMUFLG = 0xFF;
	
		CPMUPROT = 0x00U;	/* Enable protection of clock configuration registers */	
					 
		/* Common initialization of the CPU registers */
		/* CPMUINT: LOCKIE=0,OSCIE=0 */
		CPMUINT &= (UINT8)(~(UINT8)0x12U);	
					 
		/* CPMULVCTL: LVIE=0 */
		/* Low-Voltage Interrupt disable */
		CPMULVCTL &= (UINT8)(~(UINT8)0x02U);
							   
		/* IRQCR: IRQEN=0 */
		/* disable IRQ */
		IRQCR &= (UINT8)(~(UINT8)0x40U);
		
		/*Disable ECLK output, Disable ECLK x 2 output*/
		ECLKCTL = 0xC0;  
		   
#else
   #error "MAC SYS_CLOCK_SOURCE is NOT defined !"    /* system clock Defines not found! */     
#endif

}

/*****************************************************************************
** End File
*****************************************************************************/

